nrfx_uarte.c 21 KB

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  1. /**
  2. * Copyright (c) 2015 - 2019, Nordic Semiconductor ASA
  3. *
  4. * All rights reserved.
  5. *
  6. * Redistribution and use in source and binary forms, with or without modification,
  7. * are permitted provided that the following conditions are met:
  8. *
  9. * 1. Redistributions of source code must retain the above copyright notice, this
  10. * list of conditions and the following disclaimer.
  11. *
  12. * 2. Redistributions in binary form, except as embedded into a Nordic
  13. * Semiconductor ASA integrated circuit in a product or a software update for
  14. * such product, must reproduce the above copyright notice, this list of
  15. * conditions and the following disclaimer in the documentation and/or other
  16. * materials provided with the distribution.
  17. *
  18. * 3. Neither the name of Nordic Semiconductor ASA nor the names of its
  19. * contributors may be used to endorse or promote products derived from this
  20. * software without specific prior written permission.
  21. *
  22. * 4. This software, with or without modification, must only be used with a
  23. * Nordic Semiconductor ASA integrated circuit.
  24. *
  25. * 5. Any software provided in binary form under this license must not be reverse
  26. * engineered, decompiled, modified and/or disassembled.
  27. *
  28. * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
  29. * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  30. * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
  31. * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
  32. * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  33. * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  34. * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35. * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  36. * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
  37. * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  38. *
  39. */
  40. #include <nrfx.h>
  41. #if NRFX_CHECK(NRFX_UARTE_ENABLED)
  42. #if !(NRFX_CHECK(NRFX_UARTE0_ENABLED) || \
  43. NRFX_CHECK(NRFX_UARTE1_ENABLED) || \
  44. NRFX_CHECK(NRFX_UARTE2_ENABLED) || \
  45. NRFX_CHECK(NRFX_UARTE3_ENABLED))
  46. #error "No enabled UARTE instances. Check <nrfx_config.h>."
  47. #endif
  48. #include <nrfx_uarte.h>
  49. #include "prs/nrfx_prs.h"
  50. #include <hal/nrf_gpio.h>
  51. #define NRFX_LOG_MODULE UARTE
  52. #include <nrfx_log.h>
  53. #define EVT_TO_STR(event) \
  54. (event == NRF_UARTE_EVENT_ERROR ? "NRF_UARTE_EVENT_ERROR" : \
  55. "UNKNOWN EVENT")
  56. #define UARTEX_LENGTH_VALIDATE(peripheral, drv_inst_idx, len1, len2) \
  57. (((drv_inst_idx) == NRFX_CONCAT_3(NRFX_, peripheral, _INST_IDX)) && \
  58. NRFX_EASYDMA_LENGTH_VALIDATE(peripheral, len1, len2))
  59. #if NRFX_CHECK(NRFX_UARTE0_ENABLED)
  60. #define UARTE0_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE0, __VA_ARGS__)
  61. #else
  62. #define UARTE0_LENGTH_VALIDATE(...) 0
  63. #endif
  64. #if NRFX_CHECK(NRFX_UARTE1_ENABLED)
  65. #define UARTE1_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE1, __VA_ARGS__)
  66. #else
  67. #define UARTE1_LENGTH_VALIDATE(...) 0
  68. #endif
  69. #if NRFX_CHECK(NRFX_UARTE2_ENABLED)
  70. #define UARTE2_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE2, __VA_ARGS__)
  71. #else
  72. #define UARTE2_LENGTH_VALIDATE(...) 0
  73. #endif
  74. #if NRFX_CHECK(NRFX_UARTE3_ENABLED)
  75. #define UARTE3_LENGTH_VALIDATE(...) UARTEX_LENGTH_VALIDATE(UARTE3, __VA_ARGS__)
  76. #else
  77. #define UARTE3_LENGTH_VALIDATE(...) 0
  78. #endif
  79. #define UARTE_LENGTH_VALIDATE(drv_inst_idx, length) \
  80. (UARTE0_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \
  81. UARTE1_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \
  82. UARTE2_LENGTH_VALIDATE(drv_inst_idx, length, 0) || \
  83. UARTE3_LENGTH_VALIDATE(drv_inst_idx, length, 0))
  84. typedef struct
  85. {
  86. void * p_context;
  87. nrfx_uarte_event_handler_t handler;
  88. uint8_t const * p_tx_buffer;
  89. uint8_t * p_rx_buffer;
  90. uint8_t * p_rx_secondary_buffer;
  91. volatile size_t tx_buffer_length;
  92. size_t rx_buffer_length;
  93. size_t rx_secondary_buffer_length;
  94. nrfx_drv_state_t state;
  95. } uarte_control_block_t;
  96. static uarte_control_block_t m_cb[NRFX_UARTE_ENABLED_COUNT];
  97. static void apply_config(nrfx_uarte_t const * p_instance,
  98. nrfx_uarte_config_t const * p_config)
  99. {
  100. if (p_config->pseltxd != NRF_UARTE_PSEL_DISCONNECTED)
  101. {
  102. nrf_gpio_pin_set(p_config->pseltxd);
  103. nrf_gpio_cfg_output(p_config->pseltxd);
  104. }
  105. if (p_config->pselrxd != NRF_UARTE_PSEL_DISCONNECTED)
  106. {
  107. nrf_gpio_cfg_input(p_config->pselrxd, NRF_GPIO_PIN_PULLUP);
  108. }
  109. nrf_uarte_baudrate_set(p_instance->p_reg, p_config->baudrate);
  110. nrf_uarte_configure(p_instance->p_reg, p_config->parity, p_config->hwfc);
  111. nrf_uarte_txrx_pins_set(p_instance->p_reg, p_config->pseltxd, p_config->pselrxd);
  112. if (p_config->hwfc == NRF_UARTE_HWFC_ENABLED)
  113. {
  114. if (p_config->pselcts != NRF_UARTE_PSEL_DISCONNECTED)
  115. {
  116. nrf_gpio_cfg_input(p_config->pselcts, NRF_GPIO_PIN_NOPULL);
  117. }
  118. if (p_config->pselrts != NRF_UARTE_PSEL_DISCONNECTED)
  119. {
  120. nrf_gpio_pin_set(p_config->pselrts);
  121. nrf_gpio_cfg_output(p_config->pselrts);
  122. }
  123. nrf_uarte_hwfc_pins_set(p_instance->p_reg, p_config->pselrts, p_config->pselcts);
  124. }
  125. }
  126. static void interrupts_enable(nrfx_uarte_t const * p_instance,
  127. uint8_t interrupt_priority)
  128. {
  129. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX);
  130. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX);
  131. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ERROR);
  132. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_RXTO);
  133. nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK |
  134. NRF_UARTE_INT_ENDTX_MASK |
  135. NRF_UARTE_INT_ERROR_MASK |
  136. NRF_UARTE_INT_RXTO_MASK);
  137. NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number((void *)p_instance->p_reg),
  138. interrupt_priority);
  139. NRFX_IRQ_ENABLE(nrfx_get_irq_number((void *)p_instance->p_reg));
  140. }
  141. static void interrupts_disable(nrfx_uarte_t const * p_instance)
  142. {
  143. nrf_uarte_int_disable(p_instance->p_reg, NRF_UARTE_INT_ENDRX_MASK |
  144. NRF_UARTE_INT_ENDTX_MASK |
  145. NRF_UARTE_INT_ERROR_MASK |
  146. NRF_UARTE_INT_RXTO_MASK);
  147. NRFX_IRQ_DISABLE(nrfx_get_irq_number((void *)p_instance->p_reg));
  148. }
  149. static void pins_to_default(nrfx_uarte_t const * p_instance)
  150. {
  151. /* Reset pins to default states */
  152. uint32_t txd;
  153. uint32_t rxd;
  154. uint32_t rts;
  155. uint32_t cts;
  156. txd = nrf_uarte_tx_pin_get(p_instance->p_reg);
  157. rxd = nrf_uarte_rx_pin_get(p_instance->p_reg);
  158. rts = nrf_uarte_rts_pin_get(p_instance->p_reg);
  159. cts = nrf_uarte_cts_pin_get(p_instance->p_reg);
  160. nrf_uarte_txrx_pins_disconnect(p_instance->p_reg);
  161. nrf_uarte_hwfc_pins_disconnect(p_instance->p_reg);
  162. if (txd != NRF_UARTE_PSEL_DISCONNECTED)
  163. {
  164. nrf_gpio_cfg_default(txd);
  165. }
  166. if (rxd != NRF_UARTE_PSEL_DISCONNECTED)
  167. {
  168. nrf_gpio_cfg_default(rxd);
  169. }
  170. if (cts != NRF_UARTE_PSEL_DISCONNECTED)
  171. {
  172. nrf_gpio_cfg_default(cts);
  173. }
  174. if (rts != NRF_UARTE_PSEL_DISCONNECTED)
  175. {
  176. nrf_gpio_cfg_default(rts);
  177. }
  178. }
  179. nrfx_err_t nrfx_uarte_init(nrfx_uarte_t const * p_instance,
  180. nrfx_uarte_config_t const * p_config,
  181. nrfx_uarte_event_handler_t event_handler)
  182. {
  183. NRFX_ASSERT(p_config);
  184. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  185. nrfx_err_t err_code = NRFX_SUCCESS;
  186. if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED)
  187. {
  188. err_code = NRFX_ERROR_INVALID_STATE;
  189. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  190. __func__,
  191. NRFX_LOG_ERROR_STRING_GET(err_code));
  192. return err_code;
  193. }
  194. #if NRFX_CHECK(NRFX_PRS_ENABLED)
  195. static nrfx_irq_handler_t const irq_handlers[NRFX_UARTE_ENABLED_COUNT] = {
  196. #if NRFX_CHECK(NRFX_UARTE0_ENABLED)
  197. nrfx_uarte_0_irq_handler,
  198. #endif
  199. #if NRFX_CHECK(NRFX_UARTE1_ENABLED)
  200. nrfx_uarte_1_irq_handler,
  201. #endif
  202. #if NRFX_CHECK(NRFX_UARTE2_ENABLED)
  203. nrfx_uarte_2_irq_handler,
  204. #endif
  205. #if NRFX_CHECK(NRFX_UARTE3_ENABLED)
  206. nrfx_uarte_3_irq_handler,
  207. #endif
  208. };
  209. if (nrfx_prs_acquire(p_instance->p_reg,
  210. irq_handlers[p_instance->drv_inst_idx]) != NRFX_SUCCESS)
  211. {
  212. err_code = NRFX_ERROR_BUSY;
  213. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  214. __func__,
  215. NRFX_LOG_ERROR_STRING_GET(err_code));
  216. return err_code;
  217. }
  218. #endif // NRFX_CHECK(NRFX_PRS_ENABLED)
  219. apply_config(p_instance, p_config);
  220. p_cb->handler = event_handler;
  221. p_cb->p_context = p_config->p_context;
  222. if (p_cb->handler)
  223. {
  224. interrupts_enable(p_instance, p_config->interrupt_priority);
  225. }
  226. nrf_uarte_enable(p_instance->p_reg);
  227. p_cb->rx_buffer_length = 0;
  228. p_cb->rx_secondary_buffer_length = 0;
  229. p_cb->tx_buffer_length = 0;
  230. p_cb->state = NRFX_DRV_STATE_INITIALIZED;
  231. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  232. __func__,
  233. NRFX_LOG_ERROR_STRING_GET(err_code));
  234. return err_code;
  235. }
  236. void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance)
  237. {
  238. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  239. nrf_uarte_disable(p_instance->p_reg);
  240. if (p_cb->handler)
  241. {
  242. interrupts_disable(p_instance);
  243. }
  244. pins_to_default(p_instance);
  245. #if NRFX_CHECK(NRFX_PRS_ENABLED)
  246. nrfx_prs_release(p_instance->p_reg);
  247. #endif
  248. p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
  249. p_cb->handler = NULL;
  250. NRFX_LOG_INFO("Instance uninitialized: %d.", p_instance->drv_inst_idx);
  251. }
  252. nrfx_err_t nrfx_uarte_tx(nrfx_uarte_t const * p_instance,
  253. uint8_t const * p_data,
  254. size_t length)
  255. {
  256. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  257. NRFX_ASSERT(p_cb->state == NRFX_DRV_STATE_INITIALIZED);
  258. NRFX_ASSERT(p_data);
  259. NRFX_ASSERT(length > 0);
  260. NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length));
  261. nrfx_err_t err_code;
  262. // EasyDMA requires that transfer buffers are placed in DataRAM,
  263. // signal error if the are not.
  264. if (!nrfx_is_in_ram(p_data))
  265. {
  266. err_code = NRFX_ERROR_INVALID_ADDR;
  267. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  268. __func__,
  269. NRFX_LOG_ERROR_STRING_GET(err_code));
  270. return err_code;
  271. }
  272. if (nrfx_uarte_tx_in_progress(p_instance))
  273. {
  274. err_code = NRFX_ERROR_BUSY;
  275. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  276. __func__,
  277. NRFX_LOG_ERROR_STRING_GET(err_code));
  278. return err_code;
  279. }
  280. p_cb->tx_buffer_length = length;
  281. p_cb->p_tx_buffer = p_data;
  282. NRFX_LOG_INFO("Transfer tx_len: %d.", p_cb->tx_buffer_length);
  283. NRFX_LOG_DEBUG("Tx data:");
  284. NRFX_LOG_HEXDUMP_DEBUG(p_cb->p_tx_buffer,
  285. p_cb->tx_buffer_length * sizeof(p_cb->p_tx_buffer[0]));
  286. err_code = NRFX_SUCCESS;
  287. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX);
  288. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
  289. nrf_uarte_tx_buffer_set(p_instance->p_reg, p_cb->p_tx_buffer, p_cb->tx_buffer_length);
  290. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STARTTX);
  291. if (p_cb->handler == NULL)
  292. {
  293. bool endtx;
  294. bool txstopped;
  295. do
  296. {
  297. endtx = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDTX);
  298. txstopped = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
  299. }
  300. while ((!endtx) && (!txstopped));
  301. if (txstopped)
  302. {
  303. err_code = NRFX_ERROR_FORBIDDEN;
  304. }
  305. p_cb->tx_buffer_length = 0;
  306. }
  307. NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
  308. return err_code;
  309. }
  310. bool nrfx_uarte_tx_in_progress(nrfx_uarte_t const * p_instance)
  311. {
  312. return (m_cb[p_instance->drv_inst_idx].tx_buffer_length != 0);
  313. }
  314. nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance,
  315. uint8_t * p_data,
  316. size_t length)
  317. {
  318. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  319. NRFX_ASSERT(m_cb[p_instance->drv_inst_idx].state == NRFX_DRV_STATE_INITIALIZED);
  320. NRFX_ASSERT(p_data);
  321. NRFX_ASSERT(length > 0);
  322. NRFX_ASSERT(UARTE_LENGTH_VALIDATE(p_instance->drv_inst_idx, length));
  323. nrfx_err_t err_code;
  324. // EasyDMA requires that transfer buffers are placed in DataRAM,
  325. // signal error if the are not.
  326. if (!nrfx_is_in_ram(p_data))
  327. {
  328. err_code = NRFX_ERROR_INVALID_ADDR;
  329. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  330. __func__,
  331. NRFX_LOG_ERROR_STRING_GET(err_code));
  332. return err_code;
  333. }
  334. bool second_buffer = false;
  335. if (p_cb->handler)
  336. {
  337. nrf_uarte_int_disable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK |
  338. NRF_UARTE_INT_ENDRX_MASK);
  339. }
  340. if (p_cb->rx_buffer_length != 0)
  341. {
  342. if (p_cb->rx_secondary_buffer_length != 0)
  343. {
  344. if (p_cb->handler)
  345. {
  346. nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK |
  347. NRF_UARTE_INT_ENDRX_MASK);
  348. }
  349. err_code = NRFX_ERROR_BUSY;
  350. NRFX_LOG_WARNING("Function: %s, error code: %s.",
  351. __func__,
  352. NRFX_LOG_ERROR_STRING_GET(err_code));
  353. return err_code;
  354. }
  355. second_buffer = true;
  356. }
  357. if (!second_buffer)
  358. {
  359. p_cb->rx_buffer_length = length;
  360. p_cb->p_rx_buffer = p_data;
  361. p_cb->rx_secondary_buffer_length = 0;
  362. }
  363. else
  364. {
  365. p_cb->p_rx_secondary_buffer = p_data;
  366. p_cb->rx_secondary_buffer_length = length;
  367. }
  368. NRFX_LOG_INFO("Transfer rx_len: %d.", length);
  369. err_code = NRFX_SUCCESS;
  370. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX);
  371. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_RXTO);
  372. nrf_uarte_rx_buffer_set(p_instance->p_reg, p_data, length);
  373. if (!second_buffer)
  374. {
  375. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STARTRX);
  376. }
  377. else
  378. {
  379. nrf_uarte_shorts_enable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
  380. }
  381. if (m_cb[p_instance->drv_inst_idx].handler == NULL)
  382. {
  383. bool endrx;
  384. bool rxto;
  385. bool error;
  386. do {
  387. endrx = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX);
  388. rxto = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_RXTO);
  389. error = nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ERROR);
  390. } while ((!endrx) && (!rxto) && (!error));
  391. m_cb[p_instance->drv_inst_idx].rx_buffer_length = 0;
  392. if (error)
  393. {
  394. err_code = NRFX_ERROR_INTERNAL;
  395. }
  396. if (rxto)
  397. {
  398. err_code = NRFX_ERROR_FORBIDDEN;
  399. }
  400. }
  401. else
  402. {
  403. nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK |
  404. NRF_UARTE_INT_ENDRX_MASK);
  405. }
  406. NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
  407. return err_code;
  408. }
  409. bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance)
  410. {
  411. return nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_ENDRX);
  412. }
  413. uint32_t nrfx_uarte_errorsrc_get(nrfx_uarte_t const * p_instance)
  414. {
  415. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_ERROR);
  416. return nrf_uarte_errorsrc_get_and_clear(p_instance->p_reg);
  417. }
  418. static void rx_done_event(uarte_control_block_t * p_cb,
  419. size_t bytes,
  420. uint8_t * p_data)
  421. {
  422. nrfx_uarte_event_t event;
  423. event.type = NRFX_UARTE_EVT_RX_DONE;
  424. event.data.rxtx.bytes = bytes;
  425. event.data.rxtx.p_data = p_data;
  426. p_cb->handler(&event, p_cb->p_context);
  427. }
  428. static void tx_done_event(uarte_control_block_t * p_cb,
  429. size_t bytes)
  430. {
  431. nrfx_uarte_event_t event;
  432. event.type = NRFX_UARTE_EVT_TX_DONE;
  433. event.data.rxtx.bytes = bytes;
  434. event.data.rxtx.p_data = (uint8_t *)p_cb->p_tx_buffer;
  435. p_cb->tx_buffer_length = 0;
  436. p_cb->handler(&event, p_cb->p_context);
  437. }
  438. void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance)
  439. {
  440. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  441. nrf_uarte_event_clear(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED);
  442. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPTX);
  443. if (p_cb->handler == NULL)
  444. {
  445. while (!nrf_uarte_event_check(p_instance->p_reg, NRF_UARTE_EVENT_TXSTOPPED))
  446. {}
  447. }
  448. NRFX_LOG_INFO("TX transaction aborted.");
  449. }
  450. void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance)
  451. {
  452. uarte_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
  453. // Short between ENDRX event and STARTRX task must be disabled before
  454. // aborting transmission.
  455. if (p_cb->rx_secondary_buffer_length != 0)
  456. {
  457. nrf_uarte_shorts_disable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
  458. }
  459. nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX);
  460. NRFX_LOG_INFO("RX transaction aborted.");
  461. }
  462. static void uarte_irq_handler(NRF_UARTE_Type * p_uarte,
  463. uarte_control_block_t * p_cb)
  464. {
  465. if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ERROR))
  466. {
  467. nrfx_uarte_event_t event;
  468. nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ERROR);
  469. event.type = NRFX_UARTE_EVT_ERROR;
  470. event.data.error.error_mask = nrf_uarte_errorsrc_get_and_clear(p_uarte);
  471. event.data.error.rxtx.bytes = nrf_uarte_rx_amount_get(p_uarte);
  472. event.data.error.rxtx.p_data = p_cb->p_rx_buffer;
  473. // Abort transfer.
  474. p_cb->rx_buffer_length = 0;
  475. p_cb->rx_secondary_buffer_length = 0;
  476. p_cb->handler(&event, p_cb->p_context);
  477. }
  478. else if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDRX))
  479. {
  480. nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDRX);
  481. size_t amount = nrf_uarte_rx_amount_get(p_uarte);
  482. // If the transfer was stopped before completion, amount of transfered bytes
  483. // will not be equal to the buffer length. Interrupted transfer is ignored.
  484. if (amount == p_cb->rx_buffer_length)
  485. {
  486. if (p_cb->rx_secondary_buffer_length != 0)
  487. {
  488. uint8_t * p_data = p_cb->p_rx_buffer;
  489. nrf_uarte_shorts_disable(p_uarte, NRF_UARTE_SHORT_ENDRX_STARTRX);
  490. p_cb->rx_buffer_length = p_cb->rx_secondary_buffer_length;
  491. p_cb->p_rx_buffer = p_cb->p_rx_secondary_buffer;
  492. p_cb->rx_secondary_buffer_length = 0;
  493. rx_done_event(p_cb, amount, p_data);
  494. }
  495. else
  496. {
  497. p_cb->rx_buffer_length = 0;
  498. rx_done_event(p_cb, amount, p_cb->p_rx_buffer);
  499. }
  500. }
  501. }
  502. if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_RXTO))
  503. {
  504. nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_RXTO);
  505. if (p_cb->rx_buffer_length != 0)
  506. {
  507. p_cb->rx_buffer_length = 0;
  508. // In case of using double-buffered reception both variables storing buffer length
  509. // have to be cleared to prevent incorrect behaviour of the driver.
  510. p_cb->rx_secondary_buffer_length = 0;
  511. rx_done_event(p_cb, nrf_uarte_rx_amount_get(p_uarte), p_cb->p_rx_buffer);
  512. }
  513. }
  514. if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDTX))
  515. {
  516. nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDTX);
  517. if (p_cb->tx_buffer_length != 0)
  518. {
  519. tx_done_event(p_cb, nrf_uarte_tx_amount_get(p_uarte));
  520. }
  521. }
  522. }
  523. #if NRFX_CHECK(NRFX_UARTE0_ENABLED)
  524. void nrfx_uarte_0_irq_handler(void)
  525. {
  526. uarte_irq_handler(NRF_UARTE0, &m_cb[NRFX_UARTE0_INST_IDX]);
  527. }
  528. #endif
  529. #if NRFX_CHECK(NRFX_UARTE1_ENABLED)
  530. void nrfx_uarte_1_irq_handler(void)
  531. {
  532. uarte_irq_handler(NRF_UARTE1, &m_cb[NRFX_UARTE1_INST_IDX]);
  533. }
  534. #endif
  535. #if NRFX_CHECK(NRFX_UARTE2_ENABLED)
  536. void nrfx_uarte_2_irq_handler(void)
  537. {
  538. uarte_irq_handler(NRF_UARTE2, &m_cb[NRFX_UARTE2_INST_IDX]);
  539. }
  540. #endif
  541. #if NRFX_CHECK(NRFX_UARTE3_ENABLED)
  542. void nrfx_uarte_3_irq_handler(void)
  543. {
  544. uarte_irq_handler(NRF_UARTE3, &m_cb[NRFX_UARTE3_INST_IDX]);
  545. }
  546. #endif
  547. #endif // NRFX_CHECK(NRFX_UARTE_ENABLED)